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Keyword: asynchronous circuit design
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Blunno, I.;
Lavagno, L.:
Deriving signal transition graphs from behavioral Verilog HDL.
1999.
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Saito, H.;
Kondratyev, A.;
Cortadella, J.;
Lavagno, L.;
Yakovlev, A.:
What is the cost of delay insensitivity?
1999.
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Goncharov, M.V.;
Klotchkov, I.V.;
Smirnov, A.B.;
Starodoubtsev, N.A.:
Timing extensions of STG model and a method to simulate timed STG behavior in VHDL environment.
1998.
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