Timing extensions of STG model and a method to simulate timed STG behavior in VHDL environment.

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Timing extensions of STG model and a method to simulate timed STG behavior in VHDL environment.

Goncharov, M.V.; Klotchkov, I.V.; Smirnov, A.B.; Starodoubtsev, N.A.

In: Proc. 1998 Int. Conf. on Application of Concurrency to System Design (CSD'98), 23-26 March 1998, Fukushima, Japan, pages 120-129. 1998.

Abstract: This paper includes an overview of the signal transition graph (STG) model extensions that make it possible to specify switching and signal propagation delays in an STG. Extended STGs are Petri nets with timed places and timed transitions. The correspondence of the STG timing models to the implementation of asynchronous circuits is studied. A method to simulate the behavior specified by consistent and bounded timed STG in VHDL environment is proposed. For illustration, a possible use of the VHDL-based STG representation in asynchronous circuit design is discussed.

Keywords: VHDL, asynchronous circuit design, signal transitions graphs, timed Petri nets, timed STGs.

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