Keyword: logic synthesis

• Khomenko, Victor; Koutny, Maciej; Yakovlev, Alex:
  Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT. 2004.

• Myers, C.J.; Rokicki, T.G.; Meng, T.H.-Y.:
  POSET timing and its application to the synthesis and verification of gate-level timed circuits. 1999.

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