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Yoneda, T.
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Little, Scott;
Seegmiller, Nicholas;
Walter, David;
Myers, Chris;
Yoneda, Tomohiro:
Verification of analog/mixed-signal circuits using labeled hybrid petri nets.
2006.
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Little, Scott;
Walter, David;
Seegmiller, Nicholas;
Myers, Chris;
Yoneda, Tomohiro:
Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets.
2004.
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Yoneda, Tomohiro:
Verification of Bounded Delay Asynchronous Circuits and Its Acceleration Techniques.
2001.
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Tomisaka, M.;
Yoneda, T.:
Partial order reduction in symbolic state space traversal using ZBDDs.
1999.
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Yoneda, T.;
Zhou, B.;
Schlingloff, B.-H.:
Verification of bounded delay asynchronous circuits with timed traces.
1999.
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Okawa, Y.;
Yoneda, T.:
Verification of schedulability of real-time systems with extended time Petri nets.
1995.
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Yoneda, T.;
Kondo, Y.;
Tohma, Y.:
On the Acceleration of Timing Verification Method Based on Time Petri Nets.
1991.
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Yoneda, T.;
Nakade, K.;
Tohma, Y.:
A Fast Timing Verification Method Based on the Independence of Units.
1988.
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