In: ICSI'90. Proceedings of the First International Conference on Systems Integration, 1990, Morristown, NJ, USA, pages 63-73. Los Alamitos, USA: IEEE Comput. Soc. Press, 1990.
Abstract: Consideration is given to the performance analysis of a RISC (reduced instruction set computer) machine (RISC/B) based on timed Petri net (TPN) models. A TPN is used to model the operation in the graph. A sequence of discrete-time Markov chains (DTMCs) is built from the TPN in the instruction execution path. The model has been validated by comparing the analytical results with those obtained from the RISC/B prototype machine. Bottlenecks in the prototype have been identified through the model and cache performance tradeoffs have been investigated from both the architectural and the organizational viewpoints.
Keywords: modelling (and) performance evaluation (of) RISC/B processor; reduced instruction set computer; timed net; discrete-time Markov chain; execution path; cache performance tradeoff.