In: Euromicro Symposium on Digital Systems Design (DSD'03), September 01 - 06, 2003, Belek-Antalya, Turkey, pages 304-311. IEEE Press, September 2003.
Abstract: In the paper, a method for formal verification of testable design is presented. As a input, a digital circuit structure at RT level designed using any DfT technique is assumed. Proposed method enables to verify testability of each element or a part of the circuit. Petri Net based model and common methods of Petri Net analysis are utilised. On the model, it is possible to prove, if a circuit element or a part of the circuit under test can be tested by a selected way - if paths, chosen for diagnostic data transport, are passable or not and if not, for what reason.