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Peng, Z.
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Karlsson, Daniel;
Eles, Petru;
Peng, Zebo:
Formal verification of component-based designs.
2007.
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Cortés, Luis Alejandro;
Eles, Petru;
Peng, Zebo:
Modeling and formal verification of embedded systems based on a Petri net representation.
2003.
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Varea, Mauricio;
Cortes, Luis Alejandro;
Al-Hashimi, Bashir;
Eles, Petru;
Peng, Zebo:
Symbolic Model Checking of Dual Transition Petri Nets.
2002.
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Cortes, Luis Alejandro;
Eles, Petru;
Peng, Zebo:
Verification of Real-Time Embedded Systems using Petri Net Models and Timed Automata.
2002.
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Cortes, L.A.;
Eles, P.;
Peng, Z.:
Definitions of equivalence for transformational synthesis of embedded systems.
2000.
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Cortes, L.A.;
Eles, P.;
Peng, Z.:
Formal coverification of embedded systems using model checking.
2000.
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Cortes, L.A.;
Eles, P.;
Peng, Z.:
Verification of embedded systems using a Petri net based representation.
2000.
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Peng, Z.:
Semantics of a Parallel Computation Model and its Applications in Digital Hardware Design.
1988.
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Kuchcinski, K.;
Peng, Z.:
Microprogramming Implementation of Timed Petri Nets (VLSI Design).
1987.
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Kuchcinski, K.;
Peng, Z.:
Parallelism Extraction from Sequential Programs for VLSI Applications.
1987.
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Peng, Z.:
Synthesis of VLSI Systems with the CAMAD Design Aid.
1986.
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Peng, Z.;
Kuchcinski, K.:
Synthesis of Control Structures from Petri Net Descriptions.
1986.
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