PhD Thesis, pages 1-224 pp.. Purdue Univ., Lafayette, IN, USA --- Ann Arbor, MI, USA: University Microfilms (Order No. 90--08, 658), 1989.
Abstract: A systematic method to construct Markov models for the reliability evaluation of processor arrays is proposed. This method is based on the premise that the fault behavior of a processor array can be modeled by a Stochastic Petri Net (SPN). However, in order to obtain a more compact representation, a set of attributes is associated with each transition in net. This representation is referred to as a Modified Stochastic Petri Net (MSPN) model. A MSPN allows the construction of the corresponding Markov model as the reachability graph is being generated. Specific reconfiguration schemes such as Successive Row Elimination (SRE), Alternate Row-Column Elimination (ARCE) and Direct Reconfiguration (DR), are analyzed in detail. Randomization techniques are used to solve the inherently large models.
Keywords: modelling (and) reliability estimation (of) fault-tolerant processor array(s); Markov model; stochastic net; reachability graph; reconfiguration scheme; successive row elimination; alternate row-column elimination; direct reconfiguration; model reduction technique; randomization technique.