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Keyword: verilog HDL

Blunno, I.; Lavagno, L.:
Deriving signal transition graphs from behavioral Verilog HDL. 1999.
Goncharov, M.V.; Klotchkov, I.V.; Smirnov, A.B.; Starodoubtcev, N.A.:
STG timing extension and simulation. 1998.

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