Escalante, M.A.

• Escalante, M.A.; Lavagno, L.; Dimopoulos, N.:
  Performance Analysis of an Arbiter using Probabilistic Timed Petri Nets. 1997.

• Escalante, Marco A.; Dimopoulos, Nikitas J.:
  Modeling Timing Correlation and the Accurate Timing Verification of Digital Interface Circuits. 1996.

• Escalante, Marco A.; Dimopoulos, Nikitas J.:
  A Probabilistic Timing Analysis for Synthesis in Microprocessor Interface Design. 1995.

• Escalante, Marco A.; Dimopoulos, Nikitas J.; Gurov, D.; Muller, H.:
  Timing Analysis for Synthesis of Hardware Interface Designs using Timing Signal Transition Graphs. 1995.

• Escalante, Marco A.; Dimopoulost, Nikitas J.; Gyuroff, Dilyan; Müller, Hausi:
  Timing Analysis for Synthesis of Hardware Interface Controllers using Timed Signal Transition Graphs. 1995.

• Gurov, D.B.; Muller, H.A.; Kapron, B.M.; Escalante, M.A.:
  Towards an optimal deadlock avoidance algorithm for flexible manufacturing systems. 1995.

• Escalante, Marco A.; Dimopoulos, Nikitas J.:
  Assessing the Feasibility of Interface Designs before their Implementation. 1995.

• Escalante, Marco A.; Dimopoulos, Nikitas J.:
  Timing analysis for synthesis in microprocessor interface design. 1994.

• Escalante, M.A.; Cheng, H. Mantis C.:
  Decomposing Signal Transition Graphs. 1993.

• Escalante, Marco A.; Dimopoulos, N. J.:
  Timed Asynchronous Interface Design in Microprocessor-based Systems. 1993.

Back to the Petri Nets Bibliography