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Castagnolo, B.
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Castagnolo, B.;
Corsi, F.;
Martino, S.:
Penelope: A Graph Based Logic Simulator for MOS Circuits.
1988.
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Castagnolo, B.;
Corsi, F.:
Evaluation of the Behaviour of Digital Circuits by Timed Petri Nets.
1986.
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Castagnolo, B.;
Corsi, F.;
Fortunato, I.;
Gubian, P.:
An Efficient Logic Simulator for VLSI Circuits Based on Petri Nets.
1984.
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Castagnolo, B.;
Corsi, F.:
Modelling Digital Circuits with Delays by Stochastic Petri Nets.
1983.
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Corsi, F.;
Castagnolo, B.:
Probabilistic Delay Evaluation in Combinational Digital Circuits by Petri Nets.
1983.
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